1. Field of the Invention
The present invention relates to programmable read only memory (PROM) integrated circuit devices and, in particular, to a single transistor cell structure for electrically erasable PROM integrated circuit devices and the method for performing erasure of data stored in such a cell.
2. Description of the Related Art
In current integrated circuit technology, there are two basic forms of erasable PROM (EPROM) devices: EPROMS on which the programmer uses impinging ultraviolet light (UV) to perform the erase function, and EEPROMS which use an electrical potential to perform erasure of the memory cells.
In each type of cell, data is represented by an electrical potential stored during the programming stage by charge injection upon a floating gate, i.e., a semiconductor region separated from the substrate and other layers in each cell by thin dielectric layers.
In the UV EPROM, the charge is removed when incident photons impart sufficient energy to stored electrons to excite them to a state where they can migrate off the gate. This requires the package to have a UV transparent window over the die, generally a quartz lid which is a high-cost item.
In an EEPROM, two general schemes exist for performing the erase function. One type of device makes use of reversible electron tunneling beneath the floating gate. By putting a relatively high potential on a superposing control gate which is opposite to the potential used during the programming mode, the stored charge is driven off the floating gate through a narrow tunnel oxide region separating the floating gate from the substrate. The other type is a triple polysilicon layer structure; the first layer provides a ground reference plate, the second is the floating gate, and the third is a program/erase control line. A second transistor, a select transistor, is used to select the bit for erasing and a voltage pulse is put on a bit line in order to draw the electrons off the floating gate. A typical circuit of the prior art for an EEPROM is shown in FIG. 1. Each of these devices exhibits inherent disadvantages.
As shown in FIG. 1(a), in both EEPROM devices, the dielectric layer, typically silicon dioxide, through which the electrons tunnel is relatively thin. A typical thin oxide in a tunneling structure may be only 110 Angstroms. The thin oxide facilitates the migration of the electrons at a low driving potential during erasure, generally about 25 volts. However, most devices have a normal operating electrical bias potential of only 5 volts or less. The relatively high voltage applied during the erase cycle results in a breakdown of these thin oxide layers. Degradation of the tunnel oxide induces leakages that affect the data retention capability of the cell. After approximately 10,000 erasures, an EEPROM is, in effect, worn out because of ultimate breakdown of the tunnel oxide.
Moreover, another disadvantage is that EEPROM devices require a "select" device to form the cell, i.e., two devices to store one bit of datum. This makes it hard to achieve high packing density desirable for small but powerful data processing machines.
In UV EPROM devices, erase time is dependent upon the erase rate factors, such as the UV spectral density and intensity, and the threshold voltage set by the sense amplifier used in conjunction with the EPROM cell array. FIG. 2 depicts the carrier action during an ERASE mode. In general, the erase process is slow, requiring minutes in a system generally operating in the nanoseconds realm.